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EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
About the Role
EnCharge AI is seeking a Senior NPU Architect to join our Architecture Team. In this role, you will collaborate with a team of NPU and system architects, hardware engineers, and software teams to define and optimize key features in our AI accelerator with the cutting-edge in-memory computing technology. You will contribute to designing a holistic AI HW/SW solution that has the best performance and efficiency on the market for the latest AI/ML workloads, such as LLMs, diffusion models, CNNs, and more.
Responsibilities
Define and develop the spec, architecture, and micro-architecture of key architecture modules (such as the in-memory compute unit, on-chip network, and memory orchestration units) based on the requirements of the workloads and software deployment flow
Contribute to the modeling of aforementioned key architecture modules in our C++ simulation framework to ensure a functional implementation of the features
Collaborate with the design verification team to deliver a strategy and infrastructure for the testing of the architecture features within said modules
Work with the software team and other architects to analyze the performance and efficiency of the architecture modules for key workloads, identify performance bottlenecks, and guide architectural decisions
Stay up to date with the latest trends and research in AI workloads, architectures, and applications to help define a path for the future generations of architectures
Qualifications
BS or MS in EE, CS, or a related field with 5-8 years of relevant experience.
Preferred: Ph.D. in a related field with 2-4 years of relevant experience.
Understanding in computer architecture, digital design, and micro-architecture concepts Familiarity with AI/ML algorithms, frameworks, and workloads
Programming experience in C/C++ and Python
Experience with HDLs such as Verilog or System Verilog
The salary range for this position is $180,000 to $240,000 USD ($175,000 to $245,000 CAD) per year. Actual compensation offered will be determined based on job-related knowledge, skills, and experience.
